The CRPR (Clock Reconvergence Pessimism Removal) method, which removes pessimistic conditions based on common points of clock paths, has been prevailing in circuit designs. For example, since the delay time does not vary at a common point which is the cross point of clock paths, the delay analysis, in which delays are calculated excluding or neglecting delays at common points, can prevent excessive design margins.
For example, Japanese Patent Application Laid-Open No. 2007-188517 (paragraph 0213) discloses a clock distributing apparatus which, through going back along a path in the direction opposite to a signal propagation direction on the basis of a net list and extracting a non-common part on finding out a common part, carries out automatically calculation with no variation of delay of a common part.